1. Field of the Invention
The present invention relates to a transistor and a method of manufacturing the same, and more particularly, to a transistor having an enlarged gate area at an upper portion thereof to achieve a stabilized electrode size, and an advantageous method of manufacturing the same.
2. Description of the Related Art
The elements of a semiconductor device are becoming more densely integrated to improve the processing speed and increase the memory capacity. Manufacturing processes for 16 M and 64 M dynamic random access memory (DRAM) devices are being replaced by 256 M manufacturing processes, and mass production techniques for 1 G devices are rapidly evolving. However, with increases in processing speed and memory capacity, the manufacturing techniques to produce the devices must take into account certain manufacturing limitations in the pursuit of delivering increasingly complex and integrated devices.
A semiconductor device is generally manufactured by forming a multi-layer structure, including dielectric layers and conductive layers, and with minute patterns having a design rule of 0.15 xcexcm or less. One of the most important goals in semiconductor design is to increase the speed of the device, which typically means reducing the size of a gate of a transistor. However, manufacturing a device having a feature size of 100 nm or less by utilizing present photolithography patterning techniques is very difficult. Accordingly, a method utilizing an SiON hard mask has been utilized to reduce the size of the gate.
FIGS. 1A-1H are schematic cross-sectional views explaining a method of manufacturing a transistor according to the conventional SiON method.
Referring to FIG. 1A, a gate oxide layer 110 having a thickness of about 100-150 xc3x85 is formed on a semiconductor substrate 100. On the gate oxide layer 110, polysilicon is deposited to a thickness of about 2500 xc3x85 to form a polysilicon layer 120, and then SiON is deposited on the polysilicon layer to a thickness of about 800 xc3x85 to form an anti-reflective layer 130. The anti-reflective layer 130 is applied in those cases where the reflectivity of an underlying layer is high, when the step coverage of the underlying layer is great, or when the critical dimension of a pattern is very small. On the anti-reflective layer 130, a photoresist is coated and then is patterned by a photolithography to form a photoresist pattern 142.
Referring to FIG. 1B, a SiON pattern 132 is formed by patterning and etching a second photoresist pattern 144, which has a reduced size when compared with the photoresist pattern 142. A dry etching process utilizing O2 may be used to form the SiON pattern 132. Generally, the photoresist is mainly composed of carbon and hydrogen, and so, the photoresist pattern is advantageously etched by oxygen, while forming CO2, CO, H2O, and the like.
Referring to FIG. 1C, the photoresist pattern 144 is removed by a strip method to form a hard mask using the SiON pattern 132 (hereinafter, referred to as SiON hard mask). The hard mask functions as an etching mask even though it is not the photoresist pattern. However, the hard mask has a higher etching selectivity than that of the photoresist pattern.
Referring to FIG. 1D, the underlying polysilicon layer 120 is etched to form a polysilicon pattern 122 by utilizing the SiON hard mask 132. In order to etch the polysilicon, a mixture of carbon tetrachloride and argon gas, a mixture of carbon tetrafluoride and oxygen gas, CF3Cl gas, a mixture of carbon fluoride-based compound and chlorine gas, etc. can be utilized.
Referring to FIG. 1E, the SiON hard mask 132 is removed and then an impurity doping process is performed utilizing the recently formed gate electrode 122 as a mask. A LDD (lightly doped drain) 102a is formed by doping an impurity having a low concentration.
Referring to FIG. 1F, a SiN layer is deposited and then an etch back process is implemented to form a spacer 150 on the side walls of the oxide pattern 122. A HDD (heavily doped drain) 102b is formed by doping an impurity having a high concentration and using the SiN spacer 150 as a mask.
Referring to FIG. 1G, a cobalt layer 160 is formed by depositing cobalt (Co) on the whole surface of the gate electrode on which the spacer 150 is formed.
Referring to FIG. 1H, a heat treatment process is performed under a temperature range of about 700-900xc2x0 C. so that the deposited cobalt reacts with the Si atoms on the underlying layer to form a CoSix compound. That is, a silicidation process is completed by respectively forming CoSix layers 124 and 114 on the oxide pattern and the substrate, except for the region where the SiN spacer 150 is formed.
By implementing a salicidation (i.e., a self-aligned silicide) process, a silicide compound can be selectively formed on a desired region. When metal compounds such as Ti, Ni, Co, etc. are deposited on a layer containing a silicon atom, and a heat treatment process is then performed, a silicide compound such as Ti-silicide, Ni-silicide or Co-silicide is formed by the interaction. After forming a dielectric layer on the silicide layer and then forming a contact hole by pattering the dielectric layer, this silicide layer can be advantageously exposed (self-aligned property). When a metallic layer is formed on the dielectric layer, the metallic layer advantageously makes contact with the silicon containing lower layer through the contact hole. Accordingly, this salicidation process is applied when manufacturing a device having a minute critical dimension.
According to the above-described method, a gate electrode having a critical dimension of about 0.10 xcexcm can be obtained. However, certain problems result when the photoresist layer is etched by using O2 as shown in FIG. 1B, since homogeneous etching is difficult because of the small pattern size.
In addition, when manufacturing a transistor with a gate electrode having a size of 0.13 xcexcm or less, a spacer is generally formed on a side wall of the gate electrode and then the silicidation process is implemented to lower the resistance of the gate electrode. At this time, the polysilicon which forms the gate electrode has a compressive stress, and the SiN compound which forms the spacer has a tensile stress, which act counter to each other. Accordingly, the metal silicide compound formed on the gate electrode receives the tensile stress of the SiN spacers formed on the side walls of the gate electrode, which stresses are confronting each other from opposite spacer directions.
U.S. Pat. No. 5,734,185 discloses a method of manufacturing a stabilized and minute gate electrode and a transistor having a gate electrode where a longitudinal length at the upper portion is longer than that at the lower portion which contacts an underlying channel region. By employing this patented method, the number of the photolithography processes for manufacturing the transistor is reduced and so the number of the masks is reduced. In addition, the capacitance of the source-drain is reduced to improve the operating efficiency of the circuit. However, it is understood that the process for the manufacture of the transistor is complicated and the formation of the channel is not advantageous.
In view of the shortcomings in the conventional art described above, it is an object of the present invention to provide a stable and minute transistor having a gate electrode in which an upper horizontal width is greater than a lower horizontal width.
Another object of the present invention is to provide a method of manufacturing a transistor in which the production costs and processing time are reduced by utilizing just one photolithography process, and thereby reducing the number of the required masks.
To accomplish the first object, the present invention provides a transistor including a substrate and a gate electrode formed on the substrate. The gate electrode has an upper portion and a lower portion, where a horizontal width of the upper portion is greater than a horizontal width of a lower portion. A spacer is formed along the side wall of the gate electrode from the upper portion to the lower portion. A first impurity doped region is formed at an upper portion of the substrate, and a second impurity doped region is formed underlying the first impurity doped region. The second impurity doped region has a impurity concentration higher than the first impurity doped region, and the second impurity doped region is narrower than the first impurity doped region.
Preferably, the ratio of the horizontal width of the upper portion and the horizontal width of the lower portion of the gate electrode is in a range of about 1.3-2.5:1, the horizontal width of the lower portion of the gate electrode is about 0.13 xcexcm or less, and the height of the gate electrode is in a range of about 1500-2500 xc3x85. More preferably, a metal silicide compound is formed on the gate electrode and the substrate.
Another object of the present invention is accomplished by providing a method of manufacturing a transistor. First, a gate electrode is formed on a substrate, with the gate electrode having an upper portion and a lower portion, and wherein a horizontal width of the upper portion is greater than a horizontal width of the lower portion. A first impurity doped region is formed in the substrate by doping a first impurity having a low concentration and using the gate electrode as a mask. Then a spacer composed of a nitride compound is formed along the entire side wall of the gate electrode. A second impurity doped region is formed in the substrate by doping a second impurity having a higher concentration than that of the first impurity, and using the spacer as a mask.
Preferably, the gate electrode is manufactured by forming, sequentially, a nitride layer, an oxide layer and a photoresist pattern on the substrate. Then, an oxide pattern is formed by etching the oxide layer using the photoresist pattern as a mask, wherein the etching exposes the nitride layer. A sacrificial spacer is then formed on a side wall of the oxide pattern. The exposed portion of the nitride layer between the sacrificial spacer is removed to expose the substrate. A thermal oxide layer is formed on the exposed portion of the substrate between the sacrificial spacer, and a polysilicon layer is deposited on the whole surface of the substrate and the oxide layer. The polysilicon layer is then planarized, and the sacrificial spacer and oxide layer are removed to realize the gate electrode structure.
The sacrificial spacer may be formed by depositing the same material as the oxide layer and implementing an etch back process until the nitride layer is exposed.
The planarization can be implemented by etching back the polysilicon to a predetermined thickness. In an alternate embodiment, the planarization may be implemented by a CMP (chemical mechanical polishing) process. If CMP is used, a nitride pattern is formed by forming another nitride layer on the oxide layer and then etching this additional nitride layer using the photoresist pattern as a mask. Then, the CMP process is implemented using the nitride layer as an etch stopping layer.
More preferably, a metal silicide compound is formed on the gate electrode and the substrate by depositing at least one metal selected from the group consisting of Co, Ti and Ni on the substrate, and then, implementing a heat treating process after implementing the second impurity doping step.
In the present invention, a transistor having a gate electrode having a wider upper portion than the lower portion thereof is advantageously manufactured, providing a stabilized transistor having a minute critical dimension.